The present invention relates to a method for manufacturing semiconductor devices, and in particular to a method for manufacturing semiconductor devices characterized by steps for forming a contact hole.
One method for increasing the level of integration of semiconductor devices having a multi-layer wiring structure is a technology referred to as self-align contact (hereinafter referred to as SAC) technology.
SAC technology is mainly used for forming self-aligning contact holes such as, for example, contact holes for a DRAM bit line contact. An example of a method for forming a contact hole using SAC technology will be briefly described in the following.
First, a nitride film pattern (for example, a silicon nitride film) is formed ranging from the surface of gate electrode patterns formed adjacently on the upper part of a substrate, to the surface of the substrate between the electrodes.
This nitride film pattern will later function as an etching prevention film highly resistant to an etching method at the time of forming a contact hole using the SAC technology.
Next, an interlayer insulation film and resist patterns for forming a hole are sequentially formed on a sample having this nitride film.
Etching for forming a contact hole using the SAC technology is then carried out under highly selective conditions between the interlayer insulation film and the nitride film. At this time, the nitride film is made to function as an etching prevention film.
As a result, the etching process can be selectively stopped by the nitride film, and a specified contact hole can be therefore formed.
In this way, the diameter of an opening of the contact hole formed by this etching is determined by gate electrode patterns in a self-aligned manner. As a result, the contact hole can be formed in an easily controllable manner and the level of integration for semiconductor devices can be increased.
However, various problems such as the following examples arise at the time of forming a contact hole using the above-mentioned SAC technology.
(1) In order to prevent a gate electrode from being etched or exposed, an etching selectivity ratio of the nitride film covering the gate electrode to the interlayer insulation film is satisfactorily high at a flat section. However, the etching selectivity ratio at a grooved section defined by the crossing of an upper surface and a side surface of the gate electrodes formed below the contact hole is decreased to approximately ⅓ of that of the flat section.
(2) When the shape of the gate electrode patterns is uneven, the thickness of the nitride film formed on the gate electrode may also become uneven.
In this manner, in case of (1) or (2), the nitride film is undesirably etched and the shoulder section of the gate electrode may be exposed. As a result, wiring metal is embedded in the contact hole where the gate electrode is exposed, and a short-circuit failure therefore occurs at the gate electrode.
(3) Dry etching, etc. over an interlayer insulation film with a high aspect ratio may be carried out under the condition where a selectivity ratio of a nitride film to an interlayer insulation film is large.
In case (3), a reaction product generated by etching remains inside the contact hole to block the etching process.
Because these various problems will be more noticeable as the level of integration for semiconductor devices increases, a method capable of applying SAC technology is desired even when space between adjacent gate electrodes is limited.